//***************************************************************************
//   Copyright(c)2020, Xidian University D405.
//   All rights reserved
//
//   IP Name         :   Null
//   File name       :   cr_clk_div.v
//   Module name     :   cr_clk_div
//   Author          :   Wang Zekun
//   Date            :   2022/06/30
//   Version         :   v1.0
//   Verison History :   v1.0/
//   Edited by       :   Wang Zekun
//   Modification history : v1.0 Initial revision
//
// ----------------------------------------------------------------------------
// Version 1.0       Date(2022/06/30)
// Abstract : Hardforward DMA unit configure interface
//
//-----------------------------------------------------------------------------
// Programmer's model
//
//-----------------------------------------------------------------------------
//interface list :
//                

module cr_clk_div (
    input  wire                           clk_i ,
    input  wire                           resetn_i,
    output wire                           clk_o
  );
  reg clk_en;
  always @(posedge clk_i or negedge resetn_i) begin
    if (~resetn_i) begin
      clk_en <= 1'b0;
    end
    else begin
      clk_en <= ~clk_en;
    end
  end
  PREICG_X1B_A12PP140ZTS_C35 clk_gate ( .CK(clk_i), .E(clk_en), .SE(1'b0), .ECK(clk_o) );
endmodule
